CHANDLER, AZ—Intel’s in a critical stage in its storied history—in a fiscal and technical slump, and in the midst of its biggest reorganization ever. But it’s also seeing historic outside investment: The US government, Nvidia, and Softbank have all put billions in a vote of confidence for the iconic chip maker. It’s a time of great change for Team Blue. But that also means a lot is riding on the success of its next-generation compute platform unveiled today, dubbed “Panther Lake,” and its next-gen process technology, 18A—and all eyes are on Intel.
Panther Lake is, on the client-compute side of things, a mobile chip platform first and foremost. Intel has classified Panther Lake as a refinement of two families of mobile CPU that came before: the energy-efficiency-minded “Lunar Lake” (a darling of long-battery-life x86 laptops, better known as the Core Ultra 200V series) and the more performance-oriented “Arrow Lake,” which tends to appear in bigger, peppier machines, often paired with a discrete GPU.
(Credit: Intel)
In a nutshell, Intel maintains that Panther Lake merges Lunar Lake’s power efficiency and the compute-performance moxie of Arrow Lake-H, without compromising on either front. The chip will feature up to 16 next-generation Performance, Efficient, and Low-Power Efficient cores, an updated integrated Xe graphics tile, an updated neural processing unit (NPU), and a heap of AI-minded enhancements. Panther Lake will deliver a broad menu of chip variants for PC makers to choose from, but the boldest claim of all—“50% more CPU and GPU performance than Lunar Lake without compromising power efficiency”—is what makes us sit up and take notice.
Taken together, it looks like just the kind of chip that a keen observer would cook up in the interest of getting Intel back on track—if the chip maker can make a go of it. At Intel’s Tech Tour in Chandler, Ariz., last week, outlining Panther Lake’s architecture, Jim Johnson, Senior VP of Intel’s Client Computing Group, noted that Panther Lake “will be the most broadly adopted AI PC platform Intel has ever offered.” If that’s the case, it will need to deliver the goods.
The Basics: 18A Ascendant
Panther Lake’s CPU portion will be built on 18A, which Intel dubs its 2nm-equivalent process technology. (Intel followers know that the names of Intel’s last few process technologies, such as Intel 3 and Intel 7, no longer bear a strict relationship to the transistor measurements of the past.) This will be the first deployment of 18A, alongside the “Clearwater Forest” data-center silicon that was also detailed as part of this launch. Intel’s predecessor for low-power laptop CPUs, Lunar Lake (aka the Core Ultra 200V series), exists as relatively few different chip models; Intel notes that Panther Lake will scale out the variety and grade of chips available much more widely.
(Credit: Intel)
The CPU portion of Panther Lake will use the new 18A process, but given the tiled nature of modern CPUs, the rest of the processor is not made on 18A. TSMC will continue to make the platform control tile, while the two versions of the GPU tile (more about which in a moment) will be made by Intel using Intel 3 (the four-core tile) or TSMC (the 12-graphics-core tile). In its construction, Panther Lake will make use of the mature Foveros-S 2.5D packaging technology to tie the die together. A Scalable Fabric Gen 2 will underlie the chip’s connections, and the GPU tile on the chip will be situated separate from the compute tile. This is made easier by the new Scalable Fabric. This separation gives Intel’s chip designers more design flexibility and helps Intel scale the graphics performance within the Panther Lake line, by enabling the easier integration of different versions of the Xe on-chip graphics.
(Credit: Intel)
As for 18A itself, Intel emphasized two key innovations with the process technology: RibbonFET and PowerVia. These are two key enabling technologies that, Intel says, are at the center of 18A’s tighter transistor density and greater efficiency.
(Credit: Intel)
In a nutshell, the now-well-known FinFET (fin field-effect transistor) tech incorporated a 3D design into transistors, diverging from planar design. FinFET incorporated a fin-shaped “channel” in the transistor for the electrical current that wrapped around the transistor gate to reduce signal leakage. (Signal leakage is a big obstacle in compacting transistors too densely within a chip.) FinFET technology came in around a decade ago and is now the industry standard, with billions of FinFET transistors firing away inside the CPU in a typical laptop.
One main limit to scaling down transistors in a CPU is that leakage at the gate. The way forward for the next decade, according to Intel, is RibbonFET, or “gate all around,” in which the transistor gate is sheathed entirely in a microthin sheet to further contain leakage. This gives designers more flexibility, and enhances gate control.
(Credit: Intel)
Intel dubbed RibbonFET the “ultimate transistor” in its presentations and points out that it will be first in the world with a foundry node employing both it and PowerVia, the other key enabling tech.
As for PowerVia, the TL;DR version of the tech is that it involves delivering power through the back side of the die. Power and signal lines have different requirements, and putting the power lines on the backside, to bring power from below, through the package to the transistors, allows for the signal lines to be more spread out. Backside power also reduces power loss from the package.
(Credit: Intel)
The traditional concern is that backside power can be expensive to implement. The 18A architecture, however, was optimized for backside power right from the start. Intel claims that the use of PowerVia enables significant increases in performance per watt versus Intel 3 (the preceding process tech), as well as substantively denser chips.
One of Intel’s emphases throughout its Tech Tour presentations was that this cutting-edge process tech isn’t being “fabbed out” to outside foundries. Wafers on the 18A process are being manufactured in the US, at facilities in Arizona and Oregon. Indeed, the day of this article’s publication (October 9), the chip maker is announcing that its Arizona fab at Ocotillo will be fully operational, manufacturing on 18A. (It already started in July at less than full capacity.)
(Credit: Intel)
Now, let’s look at the Panther Lake chip itself. The chip proper uses a “chiplet” style of discrete tiles to make up the key components. At the center of things will be a compute tile, with the GPU alongside (chosen according to the target segment) and a platform controller tile.
(Credit: Intel)
Memory support on Panther Lake will comprise LPDDR5x or straight DDR5. LPDDR5x will be supported at speeds up to 9,600 megatransfers per second (MT/sec) and DDR5 to 7,200MT/sec. The memory ceiling will be 96GB with LPDDR5 and 128GB with DDR5. The peak memory speeds will depend on the flavor of Panther Lake in question, however; more on that in a moment.
(Credit: Intel)
The idea behind the twin DDR options is that a PC OEM looking to integrate a Panther Lake chip can choose the right speed and tech, appropriate for the system limits and goals it is trying to achieve.
The Three Broad Types of Panther Lake Chip
Intel did not share specific chip models, speeds, or feeds for Panther Lake processors. However, the company noted that Panther Lake processors will be divided into three broad classes, or packages, the chips will be based on; sub-gradations and specific models of the CPU will filter out under those three umbrellas. Despite the lack of chip names or numbers, Intel did note that the naming scheme would follow the recent “Core Ultra” model established with the “Meteor Lake” (Core Ultra 100 series) line of processors.
The first Panther Lake package is a basic one with eight CPU cores and a four-core integrated Xe graphics tile. The second configuration, emphasizing better multithreaded CPU performance, will be a 16-core CPU with the same graphics loadout as the first. The top bucket for Panther Lake mobile will be a 16-core CPU with a 12-core Xe graphics tile integrated.
(Credit: Intel)
The 8-Core Basic Panther Lake
The basic version of the Panther Lake processor will comprise up to four Performance cores (or P-cores) and four Low-Power Efficient cores (LPE-cores). Given Intel’s use of “up to,” presumably lower-end variants can come with fewer cores.
The peak memory speed supported will differ depending on the type of memory deployed with the chip; LPDDR5x will be limited to 6,800MT/sec, while 6,400MT/sec is the upper end for DDR5.
(Credit: Intel)
The eight-core variant of Panther Lake will feature 8MB of memory-side cache and support 12 PCI Express lanes. Like with the other two umbrella versions below, the Neural Processing Unit (NPU) will be what Intel dubs “NPU5,” rated for 50 TOPS. That is marginally higher rated than the best earlier Intel NPUs (the 48 TOPS NPU in Lunar Lake).
In terms of connectivity, the platform at this level will support up to four Thunderbolt 4 ports, two USB 3.2 ports, and eight USB 2.0 ports, as well as Wi-Fi 7 and Bluetooth 6.0. As for the integrated graphics, we referred to four graphics cores above; more precisely, the Xe3-based GPU will have four Xe cores and four ray-tracing units.
The 16-Core Middle Version of Panther Lake
Significantly beefed up in the CPU portion, Panther Lake’s “middle bucket” will consist of an up-to-16-core CPU layer with four P-cores, eight E-cores, and four LPE-cores, and support for higher memory speeds: up to 8,533MT/sec for LPDDR5x, and 7,200MT/sec for DDR5.
(Credit: Intel)
The PCI Express lane count with this tier of Panther Lake is significantly higher, with 20 PCI Express Lanes, 12 of them being PCI Express Gen 5. The remainder are Gen 4. The GPU and the NPU remain the same as in the eight-core version.
The 16-Core Graphics-Enhanced Tier
The top tier for Panther Lake will comprise an up-to-16-core CPU with a bulked-up integrated graphics portion. The 16-core layout is the same as for the middle version, as is the NPU. The PCI Express lane loadout is different, however, with 12 total lanes: eight Gen 4, and four Gen 5. And so is the memory support; here, only LPDDR5x is supported, and you will see the highest supported memory speed for Panther Lake (9,600MT/sec) only with this 16-CPU-core/12-GPU-core variant.
(Credit: Intel)
The big draw here, however, is the enhanced Xe3-based graphics: triple the number of Xe cores and ray tracing units versus the other two tiers—12 of each.
As a recap, here’s a breakdown of the three broad configurations under which Panther Lake chips will fall…
(Credit: Intel)
Intel highlighted the new architecture behind its P-cores and E-cores. The P-cores are now dubbed “Cougar Cove,” while the E-cores are now “Darkmont.” Intel outlined a long list of tweaks and optimizations with Cougar Cove and Darkmont, most of which are esoteric outside the computer engineering field. Cougar Cove, versus the previous-generation “Lion Cove” P-cores in Lunar Lake, features much more L3 cache (up to 18MB). Intel also outlined the key optimizations in the P-cores, citing better branch prediction via improved algorithms, and tweaks to memory disambiguation, allowing for more predictable performance to schedule loads.
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(Credit: Intel)
In Darkmont (the E-cores’ architecture), Intel also touts better branch prediction, along with improved instruction coverage via tweaks to the nanocode, among other enhancements.
What’s New With the Panther Lake GPU?
As noted above, the new GPU tiles, which use a new architecture called Xe3, will come in two flavors, depending on the particular Panther Lake chip package in question. One will support four Xe cores and four ray-tracing units; the other will support 12 Xe cores and 12 ray-tracing units. In the top configuration, you’ll have support for 16MB of cache, and the 12-Xe-core version of the graphics tile will be rated for up to 120 platform TOPS. (By way of comparison, the integrated graphics on Lunar Lake comprises eight Xe cores.)
The new Xe media engines will have broader codec support, as you can see in this slide below…
(Credit: Intel)
Xe2, as a refresher, had, for its time, larger ray-tracing units, enhanced vector engines, and new XMX engines. Xe2 appeared in “Battlemage” Arc discrete graphics cards like the Intel Arc B580, and in the integrated graphics of Lunar Lake, as Intel Arc Graphics. Intel notes that Xe3 GPU silicon will launch using the Arc B-series branding, the same as Battlemage, which might be initially confusing. However, the company also teased something it referred to as “Xe3P,” which it will launch in a future “significantly advanced” product. Xe3P will presumably move on from the B-series branding, but Intel declined to elaborate further on it.
(Credit: Intel)
According to Intel, the new third-gen Xe in Panther Lake will increase the L2 cache from 8MB to 16MB, reducing traffic that hits the memory interface by as much as 36%. The graphics core will feature eight 512-bit vector engines and the same number of 2,048-bit XMX engines.
As part of its presentation on Xe3, Intel gave an interesting demo of what it dubbed “per-pixel AI” to generate an image, as opposed to traditional texturing. In this model, a Neural Radiance Field (NeRF) in five dimensions—position and direction, in addition to height, width, and depth—uses two flat images as source material. Rays passing through the two images, set perpendicular to each other, interpret what a given pixel should look like. This kind of efficient AI-based pixel rendering could come into play with the additional AI horsepower brought to bear with chips like Panther Lake, and continue a move away from reliance on traditional rasterization, in the same way that ray tracing has co-existed with rasterization for some time.
(Credit: Intel)
What’s New With the Panther Lake NPU?
The NPU, meanwhile, is rated for 50 TOPS, while adding FP8 support. That may not sound like much of an advance in these days of 50 TOPS NPUs from the likes of AMD, the 48 TOPS in Lunar Lake’s NPU, and the announced 80 TOPS NPUs in the Snapdragon X2 Elite family coming next year. But it is a significant uptick (3.8 times) over the relatively bigger TOPS count in the merely “token” NPUs of Arrow Lake-H.
(Credit: Intel)
As noted earlier, Intel refers to the NPU here as NPU5. NPU4 is what appeared in Lunar Lake, featuring 12 shave DSPs, six neural compute engines, and an efficient, optimized MAC array. (The MAC array is a collection of cells that perform very large matrix multiplication.) With NPU5, the biggest change is with further refinements to the MAC array. With Panther Lake, Intel claims it has doubled the MACs per unit area, which should translate into higher NPU performance per unit area. Indeed, Intel touts 40% better TOPS per unit area over the Lunar Lake NPU, which it attributes mostly to the MAC array tweaks.
With Panther Lake’s NPU5, the addition of native FP8 data-type support is another AI processing enhancement, for when you don’t need the finer-grained accuracy of FP16. This use of quantized FP8 models can allow for the use of larger models in the same environment versus FP16, increased processing speeds, or reduced memory usage, or some combination of the three.
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(Credit: Intel)
Panther Lake’s Connectivity Enhancements
At the platform level, Panther Lake supports Bluetooth 6 and Bluetooth Low Energy (LE), as well as Wi-Fi 7. However, Wi-Fi 7 has some interesting angles.
Support for Wi-Fi 7 is “Wi-Fi 7 R2”-compliant, a revision of Wi-Fi 7 that cements support for core Wi-Fi 7 features. Among them are Multi-Link Operation (MLO), in which a connection is made with multiple band types (for example, across 2.4GHz, 5GHz, and 6GHz) and data is sent over a less congested band, or across multiple bands at once for a throughput boost. Another, Multilink Reconfiguration (MLR), turns off some bands dynamically to save power; MLR manages the active links. A further enhancement was dubbed in Intel’s presentation “peer-to-peer channel coordination,” in which the platform reserves certain channels for P2P operation, so that it doesn’t interfere with traffic to and from the access point.
The Panther Lake platform also incorporates support for Wi-Fi 7’s 320MHz double channel width, WPA3 security, and the 6GHz band for newer Wi-Fi 7 and Wi-Fi 6E clients. Intel also outlined what it refers to as a STEP interface between the Wi-Fi silicon and the rest of the Panther Lake SoC. Typically, an interface capable of sustaining about a 5.5GB to 6GB/sec data rate is needed. But with extra Bluetooth, Wi-Fi, and control signaling to factor in, STEP paves a wider road, slightly exceeding requirements, to complement Wi-Fi 7.
As for Bluetooth, one of the new features touted was within Bluetooth LE Audio, called Auracast. With Auracast, more than one user can be connected using his or her own Bluetooth headset to the same audio source, allowing for multiple listeners to enjoy the same audio signal. A real-world use case might be friends or a couple watching a movie together on a laptop screen, each over his or her own Bluetooth headphones. Panther Lake will also be first to market with support for dual Bluetooth antennas, Intel claims.
As noted earlier, platform-level Thunderbolt 4 support will be standard with Panther Lake. Thunderbolt 5 incorporated in a Panther Lake PC would have to be a discrete addition, and a choice by the OEM.
So, What Performance Claims Is Intel Making Around Panther Lake?
Panther Lake shows major efficiency gains over both Lunar Lake and Arrow Lake-H, if Intel’s claims bear out. At a parallel level of multi-threaded (“MT” in the slide below) CPU performance, Panther Lake should draw roughly 30% less power than Arrow Lake. Meanwhile, at similar power-consumption levels, it should deliver more than 50% more performance than both Lunar Lake and Arrow Lake. And when running at a comparable level of power draw, in single-threaded tasks Panther Lake should deliver about 10% higher performance than Lunar Lake.
(Credit: Intel)
The improvements are starker in multithreaded workloads because of the addition of E-cores to the compute tiles. This advantage is most evident in the 16-core configurations, which add eight extra E-cores beyond what Lunar Lake offered. As for the overall SoC, Intel claims 10% lower power consumption over the already-efficient Lunar Lake, and a big 40% reduction over Arrow Lake, underscoring Panther Lake’s leap in both performance scalability and efficiency.
When Is Panther Lake Coming?
Intel noted that qualification samples were headed to partners at the time of its presentation last week (the week of September 29), and CES 2026 would be the official launch for Panther Lake, with samples of Panther Lake PCs available for review after CES.
Panther Lake-based systems should be on sale soon after that, which suggests a Q1 2026 launch. Of note, the systems running Panther Lake chips around the Tech Tour event in Chandler were either unbranded or had their chassis branding masked; no OEMs were specified yet for initial Panther Lake systems.
18A Data Center CPUs, Too: Meet ‘Clearwater Forest’
We won’t get into the data-center side of things in the same detail as Panther Lake, but at the Chandler Tech Tour, Intel outlined a parallel 18A push that is coming on the data-center side. “Clearwater Forest” is Intel’s next-generation Xeon processor family, following on from the previous-generation “Granite Rapids” and “Sierra Forest,” which, respectively, emphasized compute-intensive workloads (Granite) and performance-per-watt for high-density compute (Sierra).
(Credit: Intel)
Intel is dubbing its new server chips under the Clearwater Forest umbrella as “Xeon 6+,” and they will be the first 18A-based processors for the data center, using 18A for the CPU tiles, like with Panther Lake. The company is increasing the memory bandwidth and core counts with an ultimate selling point of increased server density. The Xeon 6+ processors will feature up to 288 Darkmont E-cores, with memory bandwidth up to 8,000MT/sec supported over DDR5.
(Credit: Intel)
Intel contextualized Xeon 6+ within the recent Xeon lineup. Third-gen Xeon was 10nm and monolithic, while the fourth and fifth generations (“Sapphire Rapids” and “Emerald Rapids”) employed Intel 7. Xeon 6 (Granite Rapids and Sierra Forest) employed P-cores and E-core compute cores, respectively, and were built on Intel 7 and 3. Xeon 6+ Clearwater Forest will employ a combination of Intel 7, 3, and 18A (the last for the compute cores), and rely on E-cores via 12 compute tiles.
The cores will all be Darkmont E-cores, in contrast to the “Crestmont” E-cores used on Sierra Forest. Intel outlined a large array of enhancements and improvements with the Darkmont cores at an architectural level; here is a quick rundown of the specs versus Crestmont…
(Credit: Intel)
Xeon 6+ will be socket-compatible with Granite Rapids. Intel expects that Clearwater Forest will be deployed in both one- and two-socket configs, which will allow for servers with up to a staggering 288 or 576 cores. It cites a 300-to-500-watt TDP range for the chips, per CPU.
The big play here, according to Intel, is power efficiency and data-center consolidation. Cramming that much more compute, at higher efficiency levels, into a data-center footprint can mean not only cost savings on power, but also the ability to install more server power in the same floor and rackspace, and within existing power-delivery constraints. Intel posed a theoretical consolidation scenario of a 70-rack, second-gen Xeon buildout from five years ago versus a potential 2026 Clearwater Forest one…
(Credit: Intel)
In short: less floor space and energy consumption needed for the same level of compute, or much more compute performance possible in the same floor space.
Intel didn’t share pricing, specs, or individual chip-model details on Xeon 6+, but the Clearwater Forest silicon will be produced in the same 18A facilities as Panther Lake.
(Note: PCMag attended Intel’s Panther Lake Tech Tour by invitation, but in keeping with our ethics policy, we have assumed all costs for travel and lodging for the conference.)
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I have been a technology journalist for almost 30 years and have covered just about every kind of computer gear—from the 386SX to 64-core processors—in my long tenure as an editor, a writer, and an advice columnist. For almost a quarter-century, I worked on the seminal, gigantic Computer Shopper magazine (and later, its digital counterpart), aka the phone book for PC buyers, and the nemesis of every postal delivery person. I was Computer Shopper’s editor in chief for its final nine years, after which much of its digital content was folded into PCMag.com. I also served, briefly, as the editor in chief of the well-known hard-core tech site Tom’s Hardware.
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